The invention relates generally to DC/DC switching regulators and, more particularly, to startup operation of DC/DC switching regulators.
DC/DC switching regulators are an important part of many power management systems. This is particularly true of power management systems in wireless communication devices, where circuit efficiency and power-packing density are important concerns. DC/DC switching regulators are closed loop systems. Voltage mode control is a popular conventional scheme for controlling DC/DC switching regulators. In conventional voltage mode control operation, an output voltage sampled from (e.g., a resistor divider) within the regulator load is compared to a voltage ramp signal. The result of this comparison is used to modulate the duty cycle of the regulator""s power switches.
The voltage ramp signal is typically generated from a phase locked loop (PLL) circuit. The PLL attempts to xe2x80x9clockxe2x80x9d in a particular reference clock frequency, and generates clock signals having frequencies at some multiple of the reference frequency. This synthesized clock signal becomes the switching clock of the DC/DC switching regulator.
One problem with conventional voltage mode control schemes is starting capability. At startup, the sampled output voltage is not within the range of normal operation specified by the voltage ramp signal. This results in the regulator power switches trying to turn on constantly, causing a large current flow which disadvantageously results in both an increased risk of device damage and decreased circuit performance.
Conventional solutions to the above-described startup problem typically use some form of soft-start charging capacitor and current source in conjunction with a bandgap referenced capacitor for selecting between a soft-start mode of operation and the normal mode of operation. If the charging capacitor is provided as an external component, then the cost and space requirements of the regulator are disadvantageously increased. If the charging capacitor is provided as an integrated component, then the die area is disadvantageously increased.
It is therefore desirable to avoid the aforementioned excessive current flow during startup of a voltage mode control DC/DC switching regulator, without requiring a charging capacitor.
The invention provides a signal that limits the duty cycle of the power regulator switches at startup. The duty cycle limit is gradually increased over time by operation of the signal, thereby advantageously avoiding excessive current flow during the period of time when the sampled output voltage has not reached the range of operation specified by the voltage ramp signal.